What the study found: A 12-bit, 10 MS/s two-step sub-ranging successive approximation register (SAR) analog-to-digital converter (ADC) using top-plate dividing was proposed. The study reports that this approach allows residue amplification within a single-stage SAR ADC, while avoiding a multi-stage design.
Why the authors say this matters: The authors say the structure removes gain and offset mismatches between coarse and fine conversions, which they present as improving robustness and linearity. They also conclude that the design is energy efficient even though it uses an analog residue amplifier.
What the researchers tested: The researchers designed and fabricated a prototype ADC in a 65 nm CMOS process. They evaluated its area, signal-to-noise and distortion ratio (SNDR), power consumption, and Walden figure of merit (FoM).
What worked and what didn't: The paper reports that the total CDAC capacitance was reduced by 86% compared with a conventional SAR ADC using the same unit-capacitor size. It also says the residue amplifier drives one-fourth of the total CDAC capacitance, which relaxes its power consumption. The prototype achieved 65.7 dB SNDR at Nyquist-rate input, used 227.7 μW from a 1.2 V supply, and reached a Walden FoM of 14.5 fJ/conversion step.
What to keep in mind: The abstract does not describe detailed limitations beyond the reported prototype scope. The results are from a specific 65 nm CMOS implementation, so no broader generalization is stated in the available summary.
Key points
- A 12-bit, 10 MS/s two-step sub-ranging SAR ADC with top-plate dividing was proposed.
- The design allows residue amplification within a single-stage SAR ADC instead of a multi-stage design.
- The total CDAC capacitance was reduced by 86% compared with a conventional SAR ADC using the same unit-capacitor size.
- The prototype achieved 65.7 dB SNDR at Nyquist-rate input and used 227.7 μW from a 1.2 V supply.
- The reported Walden figure of merit was 14.5 fJ/conversion step.
Disclosure
- Research title:
- Two-step SAR ADC reduces capacitance and power
- Authors:
- Jaegeun Song, Chaegang Lim
- Institutions:
- Samsung (South Korea), Hankuk University of Foreign Studies
- Publication date:
- 2026-03-03
- OpenAlex record:
- View
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