What the study found
The study found that a 12-bit, 10 MS/s two-step sub-ranging successive approximation register analog-to-digital converter can use top-plate dividing to enable residue amplification within a single-stage design. The authors report that this approach reduces capacitive digital-to-analog converter size and improves robustness and linearity.
Why the authors say this matters
The authors say the approach matters because it avoids the need for a multi-stage design and eliminates gain and offset mismatches between coarse and fine conversions. They conclude that the design offers competitive performance and energy efficiency even though it uses an analog residue amplifier.
What the researchers tested
The researchers proposed and fabricated a 12-bit, 10 MS/s two-step sub-ranging successive approximation register analog-to-digital converter in a 65 nm CMOS process. They evaluated a prototype that occupied 252 μm × 227 μm and measured its signal-to-noise and distortion ratio, power consumption, and Walden figure of merit.
What worked and what didn't
The design reduced the total capacitance of the capacitive digital-to-analog converter by 86% compared with a conventional successive approximation register analog-to-digital converter using the same unit-capacitor size. The residue amplifier drove only one-fourth of the total capacitive digital-to-analog converter capacitance, and the prototype achieved 65.7 dB signal-to-noise and distortion ratio at Nyquist-rate input, 227.7 μW power at 1.2 V, and a 14.5 fJ/conversion-step Walden figure of merit.
What to keep in mind
The available summary does not describe detailed experimental limitations or comparisons beyond the conventional design reference. The report is limited to the information in the abstract, so broader performance context is not provided.
Key points
- The paper proposes a 12-bit, 10 MS/s two-step sub-ranging SAR ADC with top-plate dividing.
- Top-plate dividing enables residue amplification within a single-stage SAR ADC.
- The total CDAC capacitance is reported to be 86% lower than in a conventional SAR ADC with the same unit-capacitor size.
- The residue amplifier drives one-fourth of the total CDAC capacitance.
- A 65 nm CMOS prototype achieved 65.7 dB SNDR, 227.7 μW power, and a 14.5 fJ/conversion-step FoM.
- The abstract does not describe additional limitations beyond the reported design scope.
Disclosure
- Research title:
- Top-plate dividing SAR ADC reduces capacitance and power
- Authors:
- Jaegeun Song, Chaegang Lim
- Institutions:
- Hankuk University of Foreign Studies, Samsung (South Korea)
- Publication date:
- 2026-03-03
- OpenAlex record:
- View
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